Until the 1990's, most computers utilized traditional general purpose processors (GPPs) to execute applications. In GPP architecture, primitive, low-level instructions (operations) such as add, multiply, subtract, compare, load, store for example, are implemented in simple hardware execution units, and often referred to as Arithmetic Logic Units (ALUs). These can be sequenced into a programmed set of instructions (software program) to implement a complex function. Such architecture is limited in its performance by the throughput achievable by the execution units of the GPP and the number of available operations of said units. Thus, for a complex function, several instructions are required to execute it if the number of available low-level instructions is low such as in a Reduced Instruction Set Computer (RISC), for example. Such a limitation places a great demand on the hardware and results in inefficiencies in the utilisation of the hardware. In addition, power management of such a centrally controlled architecture can be difficult. However, through the medium of software, such processors are very flexible in the applications they can execute and their general applicability renders them low cost, relatively speaking.
One solution to the performance problem associated with GPPs is the provision of hardware dedicated to execution of a specific, complex function. In general, two technology approaches have been developed to allow IC designers to develop application specific integrated circuits (ASICs). These are the “standard cell” and “gate array” technologies. In the standard cell approach, logic blocks are interconnected to provide desired functions. Typically, these blocks are primitive logic structures such as NAND or NOR gates or other simple logic blocks such as “adder” or “multiplier”. Gate array technology involves the fabrication of a large number of base wafers including identical IC elements (gates). An ASIC is formed by customising the gate array through specifying the conductive patterns to interconnect the pre-fabricated gates.
ASICs have greatly improved processing speed compared to GPPs. However, there are a number of problems associated with using standard cell or gate array technology to design ASICs which perform complicated functions. For example, since the standard cells and gate arrays are primitive or simple logic blocks for all types of applications, it takes great effort and skill to integrate these building blocks into useful ASICs. Whilst this problem has to some degree been mitigated by automated logic block layout processes, the resultant ASICs are still inflexible in their applicability. Consequently, ASICs, whilst ideal for executing specific applications, are inflexible having regard to execution of other functions and are expensive to develop compared to GPPs.
In more recent times, there has been a desire to find a middle way between the extremes of the low cost, high flexibility GPPs and the high cost, low flexibility ASICs. Other pressures such as time to market have also been motivating factors to find a new approach.
One such middle way comprises a system-on-chip (SoC) processor. In SoC design, the goal is to integrate an entire computing system on a single microchip. A SoC is constructed from pre-designed and reusable intellectual property (IP) blocks. An IP block may comprise a silicon layout of a multiplier unit, for example. The SoC system designer combines and possibly alters the IP blocks to deliver a SoC that matches a desired specification. A SoC may be any kind of static or programmable microchip.
An alternative approach is to try and take a GPP architecture and improve its performance by moving often executed instruction sequences (functions) into special hardware execution units requiring only one instruction to implement such a function. The result is an application specific instruction set processor (ASIP) which is designed to perform certain specific tasks as efficiently as possible. An ASIP sits between the high efficiency of an ASIC and the low cost of a GPP and provides a good balance of hardware and software to meet requirements such as flexibility, performance, fast time to market and power consumption. Because ASIPs are targeted mainly at embedded applications, processor simplicity is a major goal. In a typical ASIP design flow, the application software is profiled at assembler language level to detect instruction sequences (functions) that occur often and could be implemented in separate hardware execution units to improve performance.
Processor architectures for computer systems are known which comprise a GPP coupled to one or more ASIPs via a common bus. The GPP comprises a Central Processing Unit (CPU) of the system which executes a main control program of the system, whereas the ASIP executes an application specific program responsive to the CPU (GPP). Thus, logically, execution of an application is split into a data path part performed by the ASIP and a control part performed by the GPP. However, this split between these two domains may not always be so straight forward depending on the requirements of the application being executed. Situations may arise where an application specific instruction executed by an ASIP comprises a function which is also employed by the GPP.